Electronic Design

DFT Propels SoC IC Testing

The Design-for-Test (DFT) methodology is a strong driving force in the cost-effective testing of large-volume commodity items with very short life cycles, like system-on-chip (SoC) devices. It will ...
Semiconductor Engineering

DFT: Essential For Power-Aware Test

Power-aware test is a major manufacturing consideration due to the problems of increased power dissipation in various test modes, as well as test implications that come up with the usage of various ...
Electronics Weekly

Test firm intros DFT system

Test firm intros DFT systemNews from E-InSiteTeseda, an IC-test equipment startup from Portland, Oregon, has introduced the Teseda Validator 500, which it claims is the first design-for-test (DFT) ...
EDN

Moving DFT into chip design with hardware emulation

Of all the electronic design automation (EDA) tools on the market, design for test (DFT) may be the most under-appreciated; even though building testability into a chip during the design phase will ...
Electronic Design

Design-For-Test The Smart Way: dFT With A "Big T" And A "Little d"

Design-for-test, or DFT, should facilitate high-quality test, not change the design. Test techniques and strategies need to supply a high-quality test that screens out defective devices, avoiding ...
EDN

Complex SoC Testing with a Core-Based DFT Strategy

With scaling technology and increasing design sizes, power consumption during test and test data volume have grown dramatically &#8212 making it almost impossible to test an entire design once it ...
Semiconductor Engineering

How To Manage DFT For AI Chips

Semiconductor companies are racing to develop AI-specific chips to meet the rapidly growing compute requirements for artificial intelligence (AI) systems. AI chips from companies like Graphcore and ...