MIPS to Present Software-First Physical AI Design Insights at Chiplet Summit 2026

Chiplet Summit, the industry's largest chiplet event, today announced that MIPS, a GlobalFoundries company, will participate in Chiplet Summit 2026, February 17-19 at the Santa Clara Convention Center ...
EDN

Physical Design Flow Taps Partition Layout

Detailed and precise hierarchical design planning is essential to achieving closure on large designs. In this article we describe a new hierarchical design flow and its usage on a 3 million-gate chip.
Semiconductor Engineering

Hyperconvergence Of Design For Test And Physical Design

In today’s highly competitive semiconductor industry, chip-design companies strive for competitive advantages by optimizing designs for PPA (Power, Performance, Area). Along with the functional logic, ...
Electronic Design

Physical AI's Push Shifts into High Gear

What is physical AI and how does it extend edge AI running on embedded hardware? Why hardware/software co-design is vital for engineers working with physical AI. Where physical AI is headed, from ...
Semiconductor Engineering

Multiple Challenges Emerge With Physical AI System Design

Physical AI holds the promise of making everything from robots to a slew of mobile edge devices much more interactive and useful, but it will significantly alter how systems are designed, verified, ...