Verification remains the single biggest challenge in the design of system-on-chip (SoC) devices and reusable IP blocks. As designs continue to grow in size and complexity, new techniques emerge that ...
Some might say you need to be a full-fledged verification expert or specialist with experience using the latest object-oriented languages to tap into the productivity benefits of advanced verification ...
The latest VCS Verilog simulator from Synopsys contains built-in comprehensive coverage analysis. With it, design teams using VCS 6.0.1 can determine their verification quality before tapeout.
The key rule for chip design and verification is that bugs must be found and fixed as early in the development process as possible. It is often said that catching a bug at each successive project ...
Some results have been hidden because they may be inaccessible to you
Show inaccessible results