IEEE

Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation

Abstract: The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains. This paper proposes a benchmarking framework tailored specifically for ...
IEEE

Detecting Unknown Hardware Trojans in Register Transfer Level Leveraging Verilog Conditional Branching Features

Abstract: Hardware Trojans have concealed modifications to integrated circuits (ICs) that can alter their functions, performance, or security properties. Existing Trojan detection methods are designed ...
GitHub

Single-Cycle MIPS Processor on Cyclone V (5CSEMA5)

This project implements a single-cycle MIPS-style processor in Verilog and deploys it on the Cyclone V FPGA (DE1-SoC, 5CSEMA5). The design includes a fully integrated datapath and control unit capable ...
GitHub

A roadmap for learning VLSI design using verilog and HDL.

This repository provides a structured roadmap for learning VLSI Design using Verilog and HDL. It’s organized from basic to advanced concepts, with recommended resources for each level. Front-End ...